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low skew, 1-to-12 differential- to-lvcmos/lvttl fanout buffer ics83948i-147 idt? / ics? lvcmos/lvttl clock generator 1 ics83948AYI-147 rev. d april 8, 2009 general description the ics83948i-147 is a low skew, 1-to-12 differential-to-lvcmos/lvttl fanout buffer and a member of the hiperclocks? family of high performance clock solutions from idt. the ics83948i-147 has two selectable clock inputs. the clk, nclk pair can accept most standard differential input levels. the lvcmos_clk can accept lvcmos or lvttl input levels. the low impedance lvcmos/lvttl outputs are designed to drive 50 ? series or parallel terminated transmission lines. the effective fanout can be increased from 12 to 24 by utilizing the ability of the outputs to drive two series terminated lines. the ics83948i-147 is characterized at full 3.3v, full 2.5v or mixed 3.3v core/2.5v output operat ing supply modes. guaranteed output and part-to-part skew characteristics make the ics83948i-147 ideal for those clock distribution applications demanding well defined performance and repeatability. features ? twelve lvcmos/lvttl outputs ? selectable differential clk/nclk or lvcmos/lvttl clock input ? clk/nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? lvcmos_clk supports the following input types: lvcmos, lv t t l ? output frequency: 350mhz ? additive phase jitter, rms: 0.14ps (typical) ? output skew: 100ps (maximum), 3.3v5% ? part-to-part skew: 1ns (maximum), 3.3v5% ? operating supply modes: ? core/output 3.3v/3.3v 3.3v/2.5v 2.5v/2.5v ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s ics83948i-147 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 clk_sel lvcmos_clk clk nclk clk_en oe v dd gnd gnd q4 v ddo q5 gnd q6 v ddo q7 q11 v ddo q10 gnd q9 v ddo q8 gnd q0 v ddo q1 gnd q2 v ddo q3 gnd pin assignment 1 0 d q q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 clk_en clk_sel oe lvcmos_clk clk nclk block diagram
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 2 ics83948AYI-147 rev. d april 8, 2009 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function tables table 3a. clock select function table number name type description 1 clk_sel input pullup clock select input. when high, selects lvcmos_clk input. when low, selects clk/ nclk inputs. lvcmos / lvttl interface levels. 2 lvcmos_clk input pullup single-ended clock input. lvcmos/lvttl interface levels. 3 clk input pullup non-inverting differential clock input. 4 nclk input pulldown inverting differential clock input. 5 clk_en input pullup clock enable pin. lvcmos/lvttl interface levels. 6 oe input pullup output enable pin. when low, outputs are in an high-impedance state. when high, outputs are active. lvcmos/lvttl interface levels. 7v dd power power supply pin. 8, 12, 16, 20, 24, 28, 32 gnd power power supply ground. 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 q11, q10, q9, q8, q7, q6, q5, q4, q3, q2, q1, q0 output single-ended clock outputs. lvcmos/lvttl interface levels. 10, 14, 18, 22, 26, 30 v dd power output supply pins. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? c pd power dissipation capacitance (per output) 12 pf r out output impedance 5 7 12 ? control input clock 0 clk/nclk inputs selected 1 lvcmos_clk input selected
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 3 ics83948AYI-147 rev. d april 8, 2009 table 3b. clock input function table note 1: please refer to the application information section, wiring the differential input to accept single-ended levels. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c table 4b. power supply dc characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85c inputs outputs input to output mode polarity clk_sel lvcmos_clk clk nclk q[0:11] 0 ? 0 1 low differential to single-ended non-inverting 0 ? 1 0 high differential to single-ended non-inverting 0 ? 0 biased; note 1 low single-ended to single-ended non-inverting 0 ? 1 biased; note 1 high single-ended to single-ended non-inverting 0 ? biased; note 1 0 high single-ended to single-ended inverting 0 ? biased; note 1 1 low single-ended to single-ended inverting 1 0 ? ? low single-ended to single-ended non-inverting 1 1 ? ? high single-ended to single-ended non-inverting item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 73.6 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current 55 ma symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current 52 ma
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 4 ics83948AYI-147 rev. d april 8, 2009 table 4c. power supply dc characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = -40c to 85c table 4d. dc characteristics, t a = -40c to 85c note 1: outputs capable of driving 50 ? transmission lines terminated with 50 ? to v ddo /2. see parameter measurement section, output load ac test circuit diagrams. note 2: v il should not be less than -0.3v. note 3: common mode voltage is defined as v ih . symbol parameter test conditions minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current 55 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage lvcmos v dd = 3.465v 2 v dd + 0.3 v lvcmos v dd = 2.625v 1.7 v dd + 0.3 v v il input low voltage lvcmos v dd = 3.465v -0.3 0.8 v lvcmos v dd = 2.625v -0.3 0.7 v i in input current v in = v dd or v in = 3.465v or 2.625v 300 a v oh output high voltage; note 1 v ddo = 3.3v 5% i oh = -24ma 2.4 v v ddo = 2.5v 5% i oh = -15ma 1.8 v v ol output low voltage; note 1 v ddo = 3.3v 5% i ol = 24ma 0.55 v v ddo = 3.3v 5% i ol = 12ma 0.30 v v ddo = 2.5v 5% i ol = 15ma 0.6 v v pp peak-to-peak input voltage; note 2 clk/nclk v dd = 3.465v or 2.625v 0.15 1.3 v v cmr common mode input voltage; note 2, 3 clk/nclk v dd = 3.465v or 2.625v gnd + 0.5 v dd ? 0.85 v
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 5 ics83948AYI-147 rev. d april 8, 2009 ac electrical characteristics table 5a. ac characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. note 1: measured from the differential input crossing point to v ddo /2 of the output. note 2: measured from v dd /2 of the input to v ddo /2 of the output. note 3: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 4: defined as skew between outputs on different devices oper ating at the same supply voltage and with equal load condition s. using the same type of input on each device, the output is measured at v ddo /2. note 5: these parameters are guaranteed by characterization. not tested in production. note 6: setup and hold times are relative to the rising edge of the input clock. note 7: this parameter is defined in accordance with jedec standard 65. parameter symbol test conditio ns minimum typical maximum units f max output frequency 350 mhz t pd propagation delay clk/nclk; note 1 ? 350mhz 2 4 ns lvcmos_clk; note 2 ? 350mhz 2 4 ns t jit buffer additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz ? 20mhz 0.14 1 ps t sk(o) output skew; note 3, 7 measured on the rising edge @ v ddo /2 100 ps t sk(pp) part-to-part skew; note 4, 7 measured on the rising edge @ v ddo /2 1ns t r / t f output rise/fall time 0.8v to 2v 0.2 1.0 ns odc output duty cycle ? 150mhz, ref = clk/nclk 45 50 55 % t pzl, t pzh output enable time; note 5 5ns t plz, t phz output disable time; note 5 5ns t s clock enable setup time; note 6 clk_en to clk/nclk 1 ns clk_en to lvcmos_clk 0ns t h clock enable hold time; note 6 clk/nclk to clk_en 0 ns lvcmos_clk to clk_en 1ns
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 6 ics83948AYI-147 rev. d april 8, 2009 table 5b. ac characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. note 1: measured from the differential input crossing point to v ddo /2 of the output. note 2: measured from v dd /2 of the input to v ddo /2 of the output. note 3: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 4: defined as skew between outputs on different devices oper ating at the same supply voltage and with equal load condition s. using the same type of input on each device, the output is measured at v ddo /2. note 5: these parameters are guaranteed by characterization. not tested in production. note 6: setup and hold times are relative to the rising edge of the input clock. note 7: this parameter is defined in accordance with jedec standard 65. parameter symbol test conditio ns minimum typical maximum units f max output frequency 350 mhz t pd propagation delay clk/nclk; note 1 ? 350mhz 1.5 4.2 ns lvcmos_clk; note 2 ? 350mhz 1.7 4.4 ns t jit buffer additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz ? 20mhz 0.14 1 ps t sk(o) output skew; note 3, 7 measured on the rising edge @ v ddo /2 160 ps t sk(pp) part-to-part skew; note 4, 7 measured on the rising edge @ v ddo /2 2ns t r / t f output rise/fall time 0.6v to 1.8v 0.1 1.0 ns odc output duty cycle ? 150mhz, ref = clk/nclk 40 60 % t pzl, t pzh output enable time; note 5 5ns t plz, t phz output disable time; note 5 5ns t s clock enable setup time; note 6 clk_en to clk/nclk 1 ns clk_en to lvcmos_clk 0ns t h clock enable hold time; note 6 clk/nclk to clk_en 0 ns lvcmos_clk to clk_en 1ns
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 7 ics83948AYI-147 rev. d april 8, 2009 table 5c. ac characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. note 1: measured from the differential input crossing point to v ddo /2 of the output. note 2: measured from v dd /2 of the input to v ddo /2 of the output. note 3: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 4: defined as skew between outputs on different devices oper ating at the same supply voltage and with equal load condition s. using the same type of input on each device, the output is measured at v ddo /2. note 5: these parameters are guaranteed by characterization. not tested in production. note 6: setup and hold times are relative to the rising edge of the input clock. note 7: this parameter is defined in accordance with jedec standard 65. parameter symbol test conditio ns minimum typical maximum units f max output frequency 350 mhz t pd propagation delay clk/nclk; note 1 ? 350mhz 2 4 ns lvcmos_clk; note 2 ? 350mhz 2 4 ns t jit buffer additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz ? 20mhz 0.14 1 ps t sk(o) output skew; note 3, 7 measured on the rising edge @ v ddo /2 100 ps t sk(pp) part-to-part skew; note 4, 7 measured on the rising edge @ v ddo /2 1ns t r / t f output rise/fall time 0.8v to 2v 0.1 1.0 ns odc output duty cycle ? 200mhz, ref = clk/nclk 45 55 % t pzl, t pzh output enable time; note 5 5ns t plz, t phz output disable time; note 5 5ns t s clock enable setup time; note 6 clk_en to clk/nclk 1 ns clk_en to lvcmos_clk 0ns t h clock enable hold time; note 6 clk/nclk to clk_en 0 ns lvcmos_clk to clk_en 1ns
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 8 ics83948AYI-147 rev. d april 8, 2009 additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the powe r of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specif ied offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental . when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offs et from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on th e desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specific ations, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. additive phase jitter, rms @ 155.52mhz (12khz to 20mhz) = 0.14ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 9 ics83948AYI-147 rev. d april 8, 2009 parameter measureme nt information 3.3v core/3.3v lvcmos output load ac test circuit 3.3v core/2.5v lvcmos output load ac test circuit part-to-part skew 2.5v core/2.5v lvcmos output load ac test circuit differential input level output skew scope qx lvcmos gnd v dd, 1.65v5% -1.65v5% v ddo scope qx lvcmos gnd v dd -1.25v5% 1.25v5% 2.05v5% v ddo t sk(pp) v ddo 2 v ddo 2 part 1 part 2 qx qy scope qx lvcmos gnd v dd, 1.25v5% -1.25v5% v ddo v dd gnd clk nclk v cmr cross points v pp t sk(o) v ddo 2 v ddo 2 qx qy
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 10 ics83948AYI-147 rev. d april 8, 2009 parameter measurement in formation, continued 3.3v output rise/fall time propagation delay 2.5v output rise/fall time output duty cycle/pulse width/period 0.8v 2v 2v 0.8v t r t f q0:q11 nclk q0:q11 clk t pd v ddo 2 ? ? v dd 2 clk 0.6v 1.8v 1.8v 0.6v t r t f q0:q11 t period t pw t period odc = v ddo 2 x 100% t pw q0:q11
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 11 ics83948AYI-147 rev. d april 8, 2009 application information wiring the differential input to accept single ended levels figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possib le to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input vo ltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 1. single-ended signal driving differential input recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. clk input for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk input to ground. lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos output can be le ft floating. there should be no trace attached. v_ref single ended clock input v dd clk nclk r1 1k c1 0.1u r2 1k
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 12 ics83948AYI-147 rev. d april 8, 2009 differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. bo th signals must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt hiperclocks open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 2a. hiperclocks clk/nclk input driven by an idt open emitter hiperclocks lvhstl driver figure 2c. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 2e. hiperclocks clk/nclk input driven by a 3.3v hcsl driver figure 2b. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 2d. hiperclocks clk/nclk input driven by a 3.3v lvds driver figure 2f. hiperclocks clk/nclk input driven by a 2.5v sstl driver r1 50 r2 50 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt hiperclocks lvhstl driver hiperclocks input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl hiperclocks input hcsl *r3 33 *r4 33 clk nclk 2.5v 3.3v zo = 50 ? zo = 50 ? hiperclocks input r1 50 r2 50 *optional ? r3 and r4 can be 0 ? clk nclk hiperclocks input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 ? zo = 50 ? clk nclk hiperclocks sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 13 ics83948AYI-147 rev. d april 8, 2009 reliability information table 6. ja vs. air flow table for a 32 lead lqfp transistor count the transistor count for ics83948i-147 is: 1040 pin compatible with the mpc9448 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 73.6c/w 63.9c/w 60.3c/w
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 14 ics83948AYI-147 rev. d april 8, 2009 package outline and package dimension package outline - y suffix for 32 lead lqfp table 7. package dimensions for 32 lead lqfp reference document: jedec publication 95, ms-026 jedec variation: abc - hd all dimensions in millimeters symbol minimum nominal maximum n 32 a 1.60 a1 0.05 0.10 0.15 a2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 d & e 9.00 basic d1 & e1 7.00 basic d2 & e2 5.60 ref. e 0.80 basic l 0.45 0.60 0.75 0 7 ccc 0.10
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 15 ics83948AYI-147 rev. d april 8, 2009 ordering information table 8. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 83948AYI-147 ics83948ai147 32 lead lqfp tray -40 c to 85 c 83948AYI-147t ics83948ai147 32 lead lqfp 1000 tape & reel -40 c to 85 c 83948AYI-147lf ics948ai147l ?lead-free? 32 lead lqfp tray -40 c to 85 c 83948AYI-147ilft ics948ai147l ?lead-free? 32 lead lqfp 1000 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. th is product is intended for use in normal commercial and industrial applications. any other app lications, such as those requiri ng high reliability or other ext raordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer idt? / ics? lvcmos/lvttl clock generator 16 ics83948AYI-147 rev. d april 8, 2009 revision history sheet rev table page description of change date b t2 t8 1 2 7 10 features section - added lead-free bullet. pin characteristics table - changed c in from 4pf max. to 4pf typical; and added 5 ? min. and 12 ? max to r out . updated single ended signal driving differential input diagram. added recommendations for unused input and output pins. ordering information table - added lead -free part number, marking, and note. 11/21/05 c t5a t5b t6 1 5 6 7 11 12 features section - added additive phase jitter bullet. 3.3v ac characteristics table - added additive phase jitter. 3.3v ac characteristics table - added additive phase jitter. added additive phase jitter section. updated differential input clock interface section. updated reliability information. updated format throughout the datasheet. 1/15/08 d t4c t5c t8 1 4 7 9 15 features section - added mix voltage to supply voltage bullet. added mix dc characteristics power supply table. added mix ac characteristics table. parameter measurement information section - added 3.3v/2.5v lvcmos output load ac test circuit diagram. ordering information table - deleted ic s prefix from part/order number column. 4/1/09
ics83948i-147 low skew, 1-to-12 differential-t o-lvcmos/lvttl fanout buffer ? 2009 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com www.idt.com

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